1. Field of the Invention.
The invention relates to the field of CMOS processing, particularly processing for the fabrication of dynamic memory cells.
2. Prior Art.
Complementary, metal-oxide-semiconductor (CMOS) transistors also known as COS/MOS transistors are well-known in the art and are frequently used in applications requiring low power. CMOS field-effect transistors are characterized by high switching speeds and very high noise immunity over a wide range of power supply voltages. Moreover, CMOS circuits are particularly immune to "soft failures" associated with minority carriers generated by alpha particles.
One problem with CMOS circuits has been their tendency to "latch up". The numerous junctions used to form the n-type and p-type transistors cause parasitic, transistor-like, paths. When transistor-like action occurs in one of the parasitic paths, the integrated circuit is typically destroyed. One prior art technique for preventing latch-up is to form the integrated circuit in an epitaxial layer which layer is formed over a very heavily doped substrate. The presently described process employs this combination of a heavily doped substrate and more lightly doped epitaxial layer to reduce latch-up problems and sensitivity to input voltage undershoots.
The invented process is an improvement over the process described in U.S. Pat. No. 4,282,648. The closest cell structure to that fabricated with the present invention which Applicant is aware of, is described in U.S. Pat. Nos. 4,364,075 and 4,409,259. This application is assigned to the assignee of the present invention.